With the continued scaling of IC technology, due to the large amount of electronic circuits on a small area, the density of chip input/output connection pads (I/O's) continues to increase. This leads to an increasing bandwidth of interconnects between integrated circuits (IC's) and/or other system elements. For short interconnects, electrical signal lines maintain the highest capacity and speed. In order to keep up with the increasing speed and density requirements, system in a package (SIP) technology is increasingly used. This creates the need for 3-dimensional interconnects.
An example of a suitable 3-dimensional interconnect, so called “3D-Through Silicon Via” also referred to as “3D-TSV,” is disclosed in WO 2009 050207. In this approach, a ring structure is provided in a substrate wherein the ring structure is filled with a dielectric material and wherein the ring structure is surrounding an inner pillar structure made of conductive material which is functioning as the through silicon via interconnect structure. The dielectric material applied in the ring structure can be a spin-on or spray-on or Chemical Vapor Deposited (CVD) deposited polymer as well as a deposited/grown oxide or nitride. This through silicon via approach is schematically shown in FIG. 1. However even with this approach the TSV capacitance is still too high and not sufficient for certain applications. Hence there is still room to improve the TSV capacitance significantly to obtain an ultra-low capacitance TSV.